A key differentiator between the DEEP and DEEP-ER projects is the memory hierarchy: many applications increasingly suffer from the diverging growth rates of processor compute performance (fast, driven by multi/manycore) and memory/storage bandwidth (slow). To cure this imbalance, additional levels are added to the memory and storage hierarchy, similar to the way caches were introduced to processors a long time ago. I/O in particular threatens to become a severe bottleneck across many applications on the way to Exascale. Integrating fast storage class memory devices with the storage subsystem to e.g. serve as caches promises to address this problem.
Against this background, the DEEP-ER project integrates two innovative design approaches with the DEEP architecture: Non-Volatile Memory (NVM) devices attached to the compute nodes as well as Network Attached Memory (NAM). Both technologies will address the two key research areas of highly scalable parallel I/O and system resiliency. The project has implemented a tight co-design loop between hardware architects and designers and the software experts to ensure that the extended DEEP architecture can meet I/O performance and system resiliency requirements in the future.