This website uses cookies to manage authentication, navigation, and other functions. By using our website, you agree that we can place these types of cookies on your device.

View e-Privacy Directive Documents

The DEEP-ER architecture takes the Cluster-Booster concept of DEEP to the next level. An innovative two-level approach gives DEEP-ER significantly more flexibility than what can possibly be achieved in DEEP: The system components can be upgraded with better implementations or even newer technology. Apart from that the start-up costs and risks involved in producing highly specialized boards are avoided.

 

In order to achieve this, DEEP-ER uses second- generation Intel® Xeon Phi™ manycore CPUs that boot without the help of an attached Intel® Xeon® processor for the Booster part. Due to this, DEEP-ER is able to use the same interconnect network spanning both Cluster and Booster, while the DEEP prototype is based on two distinct networks.

 

Additionally, to support highly efficient I/O and fast checkpoint/restart systems, DEEP-ER evaluates novel memory technologies: non-volatile memory within the Booster nodes, and Network Attached Memory (NAM) as a shared, persistent memory resource. Read more on the memory hierarchy here.